This invention relates to an integrated injection logic circuit (I.sup.2 L circuit) and an improvement in which if the position of the formation of an electric probing test pad in an IC chip is properly selected, it is possible to enhance the electrical selection accuracy of good chips and to readily effect the faults analysis of defective chips.
A wafer obtained by integrating semiconductor elements in or on a semiconductor substrate is subjected to an electrical probing test before it is divided into individual IC chips, and marked as good and defective chips. The good chips are completed in a subsequent assembly process.
Where the IC chip suffers defects for some reason or other, a faults analysis is performed, but in an LSI chip having more than several thousands of elements therein a greater time and labor are necessary for analysis, because not only the circuit arrangement is complicated but also a wider area of the chip is tested. Although the degree of difficulty in analysis depends on the type of the circuit arrangement, if an integrated circuit of an I.sup.2 L configuration includes a feedback circuit, it is very difficult to locate any defective elements in the IC chip and to ascertain a cause for the defects through the measurement of the element characteristics.
The I.sup.2 L circuit includes normally 100 to 200 gates/mm.sup.2 and as the mask pattern design rule, for example, the following dimensions are often used: the size of contacts: 4 .mu.m.times.4 .mu.m (minimum dimension), the width of aluminium connections: 6 .mu.m and a spacing between the aluminium connections: 6 .mu.m. The connections of the high-integrated circuit are arranged very close to each other. In the faults analysis of the integrated circuit it is necessary to measure the characteristics of individual elements in the faulty chip and to cut out any desired spots or locations of the aluminium interconnection in such a high-integrated circuit. It is, therefore, very difficult to cut out any desired spots or locations of the interconnection due to the high integration of the chip. Even if this cutting operation is successfully performed, it is also very difficult to contact the tip of a rather thick probe with the spot or location of the aluminium interconnection. As a result, it follows that the reliance of the element characteristic data so obtained will be unavoidably lowered.
For this reason, test pads are conventionally provided, as required, for monitoring the characteristics of the circuits in the IC chip. The causes for faulty chips are often ascribed to the incompleteness of the element configuration occuring during the manufacturing process, such as the incomplete etching or overetching of electrode takeout contact holes and the breakage of the aluminium interconnection. The electric faults often include the deterioration of the withstanding voltage of elements, a drop of the amplification factor, the creation of a leakage current path, etc.
FIG. 1 shows a conventional I.sup.2 L circuit on which test pads are formed. The I.sup.2 L circuit is shown as a frequency division circuit having a (1/2).sup.n frequency division function and comprising flip-flops FFl to FFn for 1/2 frequency division, input and output interface circuits and some pads. The flip-flops FFl to FFn, each, comprise seven I.sup.2 L inverting gates as shown in FIG. 2. The input interface circuit is comprised of resistors R1 and R2 and NPN transistor Q1 and output interface circuit is comprised of a resistor R3 and NPN transistor Q2. The frequency division circuit further includes an injector common line 1 comprised of an aluminium connection to supply an injector current to the flip-flops FFl to FFn, injector current setting resistor Rin connected to the injector common line 1, input pad 2, output pad 3, power source pad 4 for supply of a power source V.sub.CC, ground pad 5 for ground potential GND and test pad 6. The respective pads 2 and 6 are formed to have a size enough great to permit a tip of the probe to be contacted with the pad. In the wafer state, the good and defective chips are selectively marked by checking, for example, (1) the normal or abnormal state of the signal line between the input pad 2 and the output pad 3, (2) a current value between the power source pad 4 and the ground pad 5 to see whether the consumption current is normal or not, and (3) a current value between the input pad 2 and the ground pad 5 to see whether individual elements such as resistors R1 and R2 have predetermined resistive values. Now suppose that some flip-flops are defective in the IC chip. In this case, any depective flip-flop such as the flip-flop FFl can be located by measuring the test pad 6. Since, however, the flip-flop FFl is comprised of seven I.sup.2 L inverting gates as shown in FIG. 2, it is impossible to distinguish the defective gate from the good gates. Thus, further checking is required in connection with the flip-flop FFl. If the number of pads is increased by placing a pad for each junction of the adjacent flip-flops, the faulty spots or locations can be restricted to a narrower range, but this method involves an increase in the area of the chip and an increase in the manufacturing cost of the IC. For this reason, the test pad must be connected to a circuit point effective as a faults analysis means and in this way the number of pads must be restricted to a minimum possible extent required.
The inventors have found through the faults analysis of I.sup.2 L.multidot.IC that faults often occur at each step of the manufacturing process of the IC chip and are often ascribable to the following five causes:
(1) a leakage current path formed at an electrode takeout contact portion for connecting the respective element to the aluminium interconnection;
(2) the increase of a contact resistance due to incomplete contact between the contact portion and the aluminium interconnection;
(3) the lowering of the current amplification factor of transistor;
(4) the breakage of the aluminium interconnection;
(5) the incomplete configuration of an inpurity diffusion pattern.
The cause (4) can be brought to light by taking a photograph of the interconnection pattern at a magnification of .times.100 to 10,000. The cause (5) can be ascertained under the microscopic observation. In either case, the results of these can be fed back to an improvement in the manufacturing process of the I.sup.2 L circuit. The causes (1) to (3) are judged by electric checking, because an investigation into these causes cannot be made from an external checking. The causes (1) and (2) are ascribable to the incomplete formation of the contact hole, while the cause (3) is ascribable to the causes (1) and (2). The incomplete pattern configuration of the aluminium interconnection and the consequent potential drop on the aluminium interconnection load to a possible fault. It is therefore important to clarify the faults of the chip under the faults items mentioned.
FIG. 3 shows an interconnection of respective gates in an I.sup.2 L circuit. The respective gate comprises a PNP transistor QI for injector and NPN transistor QO for signal inversion. In the I.sup.2 L circuit an injector current is normally supplied from a power source pad 4 through a resistor Rin and a common line 1 for injector to the emitters of injector PNP transistors QI. The number of contact holes through which the corresponding injectors are connected to the common line 1 is substantially equal to the number of gates in the IC chip and there exist several thousands of such contact holes. It is possible to infer any good and defective chips, as well as any causes for faults in the defective chip, by checking the common line 1 for abnormality.